? Improved glass passivation for high reliability and exceptional stability at high temperature ? High dI/dt and dV/dt capabilities ? Standard package ? Low thermal resistance ? Metric threads version available ? Types up to 1200 V VDRM/VRRM ? Designed and qualified for industrial and consumer level

These devices contain two independent positiveedge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

Features ? Buffering of inputs ? Wide working temperature range: -40?C to 85?C ?Fanout up to 10 LSTTL loads ? Significant power savings over LSTTL logic ICs Application

• Used to make alarm/tamper detect circuit
• S-R latch

Description This gadget has four separate 2-input NAND gates. In positive logic, each gate executes the Boolean function Y = A B. There are balanced CMOS push-pull outputs on this chip. The word "balanced" refers to the device's ability to sink and source equivalent currents. This device's drive capabilities may result in quick edges into mild loads, hence routing and load circumstances should be examined to avoid ringing. Furthermore, the device's outputs are capable of pushing higher currents than the device can withstand without being harmed. It is critical that the device's output power be restricted to avoid overcurrent damage. At all times, the electrical and thermal limitations established in the Absolute Maximum Ratings must be observed. Push-pull CMOS outputs that are not in use should be unplugged.