A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 ) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
Features:-
- Synchronous Counting and Asynchronous Loading
- Two Outputs for N-Bit Cascading
- Look-Ahead Carry for High-Speed Counting
- Fanout (Over Temperature Range)
- Standard Outputs 10 LSTTL Loads
- Bus Driver Outputs 15 LSTTL Loads
- Wide Operating Temperature Range ?55?C to 125?C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL?= 30%, NIH?= 30% of VCC?at VCC?= 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL?= 0.8V (Max), VIH?= 2V (Min)
- CMOS Input Compatibility, Il?
?1?A at VOL, VOH
?
Parameter | Specification |
Part Number | CD74HC192 |
Technology Family | HC |
VCC (Min) (V) | 2 |
VCC (Max) (V) | 6 |
Bits (#) | 4 |
Voltage (Nom) (V) | 3.3, 5 |
F @ nom voltage (Max) (MHz) | 28 |
ICC @ nom voltage (Max)(mA) | 0.08 |
tpd @ nom Voltage (Max) (ns) | 46 |
IOL (Max) (mA) | 5.2 |
IOH (Max) (mA) | -5.2 |
Rating | See Data Sheet |
Function | Counter |
Type | Decade |
Operating Temperature ? | ?-55 to 125 |
Package Group | PDIP|16 |
Related Document:-
?74HC192 IC Datasheet
* Product Images are shown for illustrative purposes only and may differ from actual product.