DS1225AD-150+

The DS1225AB and DS1225AD are 65,536-bit nonvolatile SRAMs that are structured as 8192 words by 8 bits. Each NV SRAM contains its own lithium energy source as well as control circuitry that constantly monitors VCC for out-of-tolerance conditions. When this occurs, the lithium energy source is automatically activated, and write protection is enabled unconditionally to avoid data corruption. The NV SRAMs can be used in place of existing 8k ? 8 SRAMs that are directly compatible with the common bytewide 28-pin DIP standard. The devices also have the same pinout as the 2764 EPROM and 2864 EEPROM, allowing for straightforward replacement while improving performance. The number of write cycles that can be performed is not limited, and no additional support circuitry is required for microprocessor connection.

The DS1230 256k Nonvolatile SRAMs have a capacity of 262,144 bits and are structured as 32,768 words by 8 bits. Each NV SRAM contains a self-contained lithium energy source and control circuitry that constantly monitors VCC for out-of-tolerance conditions. When such a circumstance happens, the lithium energy source is automatically activated, and write protection is engaged unconditionally to prevent data corruption. DIP-package DS1230 devices can be utilized in place of current 32k ? 8 static RAMs that directly comply to the common byte wide 28-pin DIP standard. The DIP devices also match the pinout of 28256 EEPROMs, allowing for direct substitution while improving performance. The Low Profile Module package of DS1230 devices is specifically suited for surface-mount applications. The amount of write cycles that can be performed is not limited, and no extra assistance circuitry is required for microprocessor connection.

The NE555 IC devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5V to 15V. With a 5-V supply, output levels are compatible with TTL inputs.