M24128-DRDW8TP/K

A 4K x 8 (32K bit) Serial Electrically Erasable PROM is the 24C32. This gadget was created for high-end, low-power uses like data collecting or personal communications. The 24C32 has an input cache with a capacity of eight 8-byte pages, or 64 bytes, allowing quick write loads. Additionally, it has a fixed 4K-bit block of ultra-high endurance memory for regularly changing data. Up to the 32K border, the 24C32 may read both randomly and sequentially. Up to eight 24C32 devices can share a bus with functional address lines, providing a maximum address space of 256K bits. This device is perfect for moderate POWER??non-volatile code and data applications thanks to advanced CMOS technology. The typical 8-pin plastic DIP and 8-pin surface mount SOIC packaging for the 24C32 are also available.   Features:- ? Operating voltage range: 4.5V to 5.5V - Maximum read current: 150 A at 5.5V - Peak write current: 3mA at 5.5V - Typical standby current: 1 A ? I2C compliant, industry-standard two-wire bus protocol with 100 kHz and 400 kHz modes ? Autonomous write cycle (including auto-erase) ? Switchable circuitry for data protection ? High Endurance Block has a guaranteed 10,000,000 Erase/Write cycles. - Guaranteed 1,000,000 E/W cycles for Standard Endurance Block ? Available in 8 byte page or byte modes. ? A 64-byte input cache with 1 page by 8 lines for quick write loads. ? Schmitt trigger with filtered inputs to reduce noise ? Ground bounce elimination by output slope control ? A typical write cycle time, byte or page, of 2 ms ? A single bus may support up to 8 chips and 256K bits of total memory. ? Protection from electrostatic discharge > 4000V ? 200-year data retention ? PDIP/SOIC 8-pin packages ? Variable temperatures Industrial (I): -40?C to +85?C Commercial (C): 0?C to +70?C

The Microchip Technology Inc. 25AA320/25LC320/25C320 (25XX320*) serial Electrically Erasable PROMs are 32 Kbit. A basic Serial Peripheral Interface (SPI) compliant serial bus is used to access the memory. A clock input (SCK) is required, as well as separate data in (SI) and data out (SO) lines. A Chip Selection (CS) input controls access to the device. The hold pin allows you to suspend communication with the gadget (HOLD). Transitions on the device's inputs will be ignored while it is stopped, excluding Chip Select, enabling the host to service higher priority interrupts. Features ? CMOS Low-Power Technology: - Maximum write current: 3 mA - Typical read current: 500 A - Typical standby current: 500 nA ? 4096 x 8 Bit Storage ? 32 bytes each page ? Maximum Write Cycle Time: 5 ms ? Erase and write cycles that are self-timed ? Write Block Protection: - Protect none, 1/4, 1/2, or the entire array. ? Integrated Write Protection: - Data protection circuitry that is switched on and off ? Latch for write enable - A write-protection pin ? Read in Sequence ? High dependability: - Endurance: 1 million E/W cycles - Data retention: more than 200 years - ESD protection: more than 4000V ? PDIP, SOIC, and TSSOP packages with 8 pins ? TSSOP Package with 14 Leads

The AT24C512C functions as a slave device and communicates with a host controller, also known as the bus master, using a straightforward two-wire digital serial interface that is I2C-compatible. On a serial bus, the master initiates and manages all read and write operations to slave devices, and both the master and slave devices are capable of sending and receiving data. Just two signal lines?Serial Clock (SCL) and Serial Data?make up the serial interface (SDA). The bilateral SDA pin is used to receive command and detailed empirical from the master as well as to transmit data back to the master, while the SCL pin is used to accept the clock signal from the master. To reduce the impact of input spikes and bus noise, the SCL and SDA pins each include Schmitt Triggers and inbuilt spike suppression filters. The Most Significant bit (MSb) is always transmitted first when sending commands or data. After eight bits (one byte) of information have been exchanged during bus communication, the receiving device must answer with an Acknowledge (ACK) or No-Acknowledge (NACK) response bit during such a ninth clock cycle (ack/nack clock cycle) produced by the master. As a result, nine clock cycles are needed to send one byte of data. There must be no gaps or interruptions throughout any data transfer operation since there are no spare clock cycles. AT24C512C-SSHD Datasheet 

The Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) on the Atmel? AT25320B/640B has 32,768-/65,536-bits and is divided into 4,096/8,192 words with 8 bits each. The device is prepared for usage in a wide range of industrial and commercial settings where moderate and low-voltage functioning are critical requirements. The 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, and 8-ball VFBGA packages for the AT25320B/640B are available in compact sizes. A 3-wire interface made up of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock is used to access and enable the AT25320B/640B. (SCK). No further erase cycle is necessary before Write since every programming cycle is fully self-timed. Programming one of the four blocks of write security into the status register activates block write protection. For added data security, separate instructions for programme enable and programme disable are given. The WP pin offers hardware data protection to guard against unintentional write attempts to the status register. Any serial communication can be halted using the HOLD pin without having to restart the serial sequence.