MAX3232 RS-232 Line Driver

The AM26C31 is an improved replacement for?AM26LS31 IC.?The AM26C31 device is a quadruple differential line receiver for balanced or unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a busorganized system. Fail-safe design specifies that if the inputs are open, the outputs always are high. The AM26C31 devices are manufactured using a BiCMOS process, which is a combination of bipolar and CMOS transistors

Features of FT232

• Single chip USB to asynchronous serial data transfer interface.

• Entire USB protocol handled on the chip. No USB specific firmware programming required.

• Fully integrated 1024 bit EEPROM storing device descriptors and CBUS I/O configuration.

• Fully integrated USB termination resistors.

• Fully integrated clock generation with no external crystal required plus optional clock output selection enabling a glue-less interface to external MCU or FPGA.

• Data transfer rates from 300 baud to 3 Mbaud (RS422, RS485, RS232) at TTL levels.

• 128 byte receive buffer and 256 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput.

MAX232 is a communication IC. It is used to convert TTL Signals to RS232 Signal and vice versa.?MAX232?provides RS-232 voltage level outputs (approx. ? 7.5 V) from a single 5 V supply via on-chip charge pumps and external capacitors. This makes it useful for implementing RS-232 in devices that otherwise do not need any voltages outside the 0 V to 5 V range, as power supply design does not need to be made more complicated just for driving the RS-232 in this case.

The receivers reduce RS-232 inputs (which may be as high as ? 25 V), to standard 5 V TTL levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of 0.5 V.

The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the band split filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.