PIC16F685-I/SP

The PIC12F675 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The data memory is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. The register file is organized as 64 x 8 in the PIC12F675 device. Each register is accessed, either directly or indirectly, through the File Select Register FSR. There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

The PIC16C711 is a low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16C711 mid-range family. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C711 microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C711 devices have 36 bytes of RAM, the PIC16C711 has 68 bytes of RAM and the PIC16C715 has 128 bytes of RAM. Each device has 13 I/O pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided.

The PIC16F628A is 18-pin Flash-based members of the versatile PIC16F628A family of low-cost, high-performance, CMOS, fullystatic, 8-bit microcontrollers. All PIC? microcontrollers employ an advanced RISC architecture. The PIC16F628A have enhanced core features, an eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available, complemented by a large register set.

The PIC16F73 is a 28/40-Pin 8-Bit CMOS FLASH Microcontrollers . The following are the features:- ? Timer0: 8-bit timer/counter with 8-bit prescaler ? Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock ? Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit