PIC18F44J10-I/P

The PIC12F675 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The data memory is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. The register file is organized as 64 x 8 in the PIC12F675 device. Each register is accessed, either directly or indirectly, through the File Select Register FSR. There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

The PIC16C57 from Microchip Technology is a family of low cost, high performance, 8-bit fully static, EPROM/ROM-based CMOS micro controllers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16C57 delivers performance in an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit micro controllers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C57 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external RESET circuitry. There are four oscillator configurations to choose from, including the power saving LP (Low Power) oscillator and cost saving RC oscillator.

The PIC16C63A devices are low cost, high performance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX mid-range family. All PIC? microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. The PIC16C63 devices have 22 I/O pins. Each device has 192 bytes of RAM. In addition, several peripheral features are available, including: three timer/ counters, two Capture/Compare/PWM modules, and two serial ports. The Synchronous Serial Port (SSP) can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus.

The PIC16C83A is 8-Bit CMOS EEPROM Microcontrollers?Transceiver. PIC16C83A microcontrollers typically achieve a 2:1 code compression and up to a 2:1 speed improvement (at 10 MHz) over other 8-bit microcontrollers in their class. The PIC16C83A has up to 68 bytes of RAM, 64 bytes of Data EEPROM memory, and 13 I/O pins. A timer/counter is also available.