PIC18LF8622-I/PT

The PIC12F509 device is low-cost, high-performance, 8-bit, fully-static, Flash-based CMOS micro controllers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are single cycle (200 ?s) except for program branches, which take two cycles. The device deliver performance an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit micro controllers in its class. The easy to use and easy to remember instruction set reduces development time significantly. It is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F505), including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The device is available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip?s price leadership in Flash programmable micro controllers, while benefiting from the Flash programmable flexibility. It is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ?C? compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM? PC and compatible machines.

The PIC16C57 from Microchip Technology is a family of low cost, high performance, 8-bit fully static, EPROM/ROM-based CMOS micro controllers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle except for program branches which take two cycles. The PIC16C57 delivers performance in an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit micro controllers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C57 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external RESET circuitry. There are four oscillator configurations to choose from, including the power saving LP (Low Power) oscillator and cost saving RC oscillator.

The PIC16C711 is a low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16C711 mid-range family. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C711 microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C711 devices have 36 bytes of RAM, the PIC16C711 has 68 bytes of RAM and the PIC16C715 has 128 bytes of RAM. Each device has 13 I/O pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided.

The PIC16F628A is 18-pin Flash-based members of the versatile PIC16F628A family of low-cost, high-performance, CMOS, fullystatic, 8-bit microcontrollers. All PIC? microcontrollers employ an advanced RISC architecture. The PIC16F628A have enhanced core features, an eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available, complemented by a large register set.